Low-voltage dynamic BiCMOS CLA circuit with carry skip using novel full-swing logic

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This paper presents novel low-voltage dynamic BiCMOS logic gates and an improved carry look-ahead (CLA) circuit with carry skip using these new dynamic BiCMOS topologies. The well-known MOS clock feedthrough effect is used to achieve full swing with substantially reduced low-to-high evaluation delay in the logic gates, thus, resulting in reduced carry propagation/bypass delay in the cascaded CLA array. Simulations at clocking frequency of 100 MHz, using 2-/spl mu/m BiCMOS process parameters and supply voltage in the range of 2-4 V displays lower gate delay and lower power dissipation compared to other recent dynamic BiCMOS logic topologies. The circuit has no dc power dissipation, race, or charge redistribution problems. An 8-b CLA with 5-b carry skip was achieved in 2.917 ns. This speed is significantly higher than other recent dynamic BiCMOS CLA designs. In addition, the new CLA circuit is more compact compared to previous dynamic BiCMOS CLA designs. A tiny chip was fabricated using the MOSIS Orbit Analog 2-/spl mu/m V-well CMOS process for the experimental verification of the new low-voltage dynamic BiCMOS topologies.