Low voltage CMOS timing generator using array of digital delay lock loops

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In this paper, Low Voltage CMOS Timing Generator Using Array of Digital Delay Lock Loops is presented. The timing generator is implemented as an array of Delay Locked Loops, providing wide operating frequency range. This architecture enables a timing generator with sub-gate delay resolution to be implemented. The proposed Delay Lock Loops use a Dual Phase and Frequency Detector along with a charge pump where the injected charge approaches zero as the loop approaches lock on the leading and the trailing edges of an input clock reference. The Delay Lock Loop lock on both the leading and trailing clock edges as dual Phase and Frequency Detector along with charge pump convert the phase difference into voltage. The start controlled dual Phase and Frequency Detector use a start-controlled circuit to provide a precise output without the locking problem. This array DLL is based on self-biased technique and achieves high process technology independence, fixed damping factor, fixed bandwidth to operating frequency range and input phase offset cancellation. The results show that the total delay time between the input and the output of the DLL (Delay Lock Loop) is one clock cycle and all of the delay cells provide precise output without false locking or harmonic locking. The simulation results show a timing jitter of less than 1pS for the DLL circuit and have very low phase sensitivity errors. The timing generator implemented as an array of Delay Locked Loops has exponentially reduced the locking time as well avoids harmonic locking.