A CMOS three-state frequency detector complementary to an enhanced linear phase detector for PLL, DLL or high frequency clock skew measurement

Abstract

A novel three state frequency detector (FD) is proposed and analysed. It complements a linear phase detector (PD). The parallel combination of these two detectors gives a new Phase-frequency detector (PFD), in which the frequency detection turns off when the phase difference is below 180 degrees. Thus, mismatches in the FD cannot affect the phase accuracy. This feature allows the designer to create a high-speed, no dead-zone wide capture range PLL, with low noise generation or sensitivity, and low power consumption. The enhanced linear PD has a higher gain at /spl plusmn/180 degrees and a better transfer function at high frequency than previous proposals. Those advantages give a better behaviour nearby /spl plusmn/180 degrees or at high frequencies, when the PD is used with the FD, in PLLs, or without the FD, like in Delay Locked Loops (DLL). It can detect phase differences between various signals selected from a broad class of waveform types. Results presented in this paper show that the proposed PD can cover a wide range of frequencies that easily reaches up to 4 GHz when implemented with TSMC 0.18 micron CMOS. The detector remains accurate and linear up to the highest experimented frequencies. Thus, it can be useful for precise analog clock skew measurements. Its simple topology uses only 24 MOS transistors that can be mostly of minimum size.