Low Power Sub-threshold Domino AND Gate

Abstract

A high performance digital system is the need of an hour, in the current scenario not only the area but the leakage power holds the key for the future devices. The development of handheld devices often gets restricted due to the limited power resources available in these devices. The conventional structure performs badly for these devices hence multiple design schemes like domino have surface for recent devices. The Domino logic circuits provide high speed operations in comparison to conventional structure. The problem of charge sharing, charge leakage in domino circuits results in improper output level which can be eliminated using Keeper and Pre-charge internal node technique. For achieving very low power all PMOS and NMOS transistors are conducted in sub threshold region. This paper has implemented ultra-low power Domino AND gate. Simulations has been done using Tanner 13 using 18u CMOS technology. A comparison has been carried out with different approaches available in literature and keeper circuit-based domino logic reveals least power consumption which makes it is suitable for ultra-low power devices.