Low power, less area, and highly efficient hybrid 1-bit full adder

Abstract

The widely used and efficient technique is to design an FA circuit using XNOR-XOR cells in the Pass transistor and CMOS hybrid logic. The performance metrics of hybrid full adders, such as power, driving capability, and power, depend highly on the XNOR-XOR circuit. The proposed FA design provides optimization with respect to speed and performance. Low load capacitance and low static power dissipation in the circuit enabled the optimized design characteristics. The proposed circuits outperform existing designs in device parameters such as device speed, total energy consumption, power, and fanout. Cadence Virtuoso is the simulation tool used for simulations and results with a 90nm model. The test outcomes show the new design outperforms other FA designs regarding speed and power. In comparison to the available FA modules, the proposed FA reduces delay by 48% and improves power and power delay products by 7% and 52%, respectively. Microwind design software is used to create layouts. The paper presents a more straightforward layout of the proposed design that takes up less area.