Low-power∕high-performance explicit-pulsed flip-flop using static latch and dynamic pulse generator

Abstract

Latches and flip-flops play important roles in the building of digital CMOS circuits. In the paper, a new low-power positive level-sensitive latch and a simple and innovative dynamic pulse generator are proposed. The pulse generator is then used with the proposed latch to create a low-power and high-performance single edge-triggered flip-flop (SETFF). The proposed positive level-sensitive latch deploys two non-precharge (static) n-stages (SN) in a true-single-phase-clocking (TSPC) scheme. We therefore named our latch SN2. This is because the TSPC latches have the advantage of single clock distribution, less clock routing area, high-speed and no clock skew. Based on the 0.18-μm single-poly six-metal CMOS technology, the SPECTRE simulation results derived for typical input activities showed that the latch can attain a maximum power saving of 29.1% when compared to other reported designs. As for our proposed flip-flop that is derived from the proposed SN2 latch with incorporation of a dynamic pulse generator circuit, it is able to outperform other reported works by about 16.2% to 67.4% for its power-delay product (PDPCQ) that is taken with respect to the clock-to-output delay. The two new designs are therefore suitable for used in low-power and high-performance CMOS VLSI/ULSI applications.