Low power consumption and low area capacitor array for 16-bit 1-MS/s SAR ADC

Abstract

A low power consumption and low area capacitor array for 16-bit 1Ms/s successive approximation register (SAR) analogue to digital converter (ADC) is presented. The new capacitor array is divided into three segments, and the bridge capacitor is integer by redundant and weight bits. The new switching method replaced the previous method of three reference levels by divided bit capacitors into two equal sub-capacitors. Moreover, through the calculation and measurement of quantization noise and thermal noise, the proposed method gives the exact capacitor array area. The number of unit capacitor used in the proposed method is 225 of one side, and it can save 99.93% area compared with conventional 16-bit capacitor array. However, energy loss of the proposed scheme is 99.5% reduced by the three segments capacitor arrays and new switching scheme. Moreover, a dynamic latch comparator with two stages of pre-amplification structure is presented. The measured differential non-linearity (DNL) and integral non-linearity (INL) are within 0.33 and 0.1793 least significant bits, respectively, and it has 15.87 effective number of bits (ENOB).