Low power and roboust FinFET SRAM cell using independent gate control

Abstract

In this paper, we propose a robust FinFET SRAM design with pMOS access transistors using independent gate (IG) control method. This design is performed by dynamically adjusting the back-gate (BG) voltages of pull-down (PD) trans istors. For generating optimum PD, BG voltages, we use an extra write driver, predischarge circuit and nMOS switches for write, hold and read operation respectively. Mixed-mode TCAD simulations for physical gate length of 22 nm, indicate that the proposed cell has the highest read SNM and writeability, and the least static power dissipation than recently reported IG cells.