Low Leakage III-V/Ge CMOS FinFET Design for High-Performance Logic Applications with High-k Spacer Technology

Abstract

We propose a novel optimized design strategy by considering the correlated effects of highk gate oxide and spacer dielectric on GIDL and DIBL for high performance nanoscale CMOS with III-V/Ge channel tri-gate FinFET structure. By investigating the transition of GIDL mechanism from vertical to lateral direction in 14-nm InAs n-FinFET and Ge p-FinFET with abrupt and high drain doping, the lateral GIDL is suppressed as 1/100 by high-k spacer with high drive current of 1 mA/um and lower leakage current than 100 nA/um which works on lower operation voltage (VDD= 0.63 V). in addition, DIBL is also suppressed below 100 mV/V by taking relatively lower-k gate oxide than the high-k spacer.