Performance Analysis of DMG-GOS Junctionless FinFET with high-k Spacer

Abstract

In this paper, the Dual Material Gate (DMG) Gate Oxide Stack (GOS) Junctionless FinFET (JLFinFET) with high-k spacer is designed and analyzed its performance for nanoscale applications. Initially, the doping is optimized and then after work function. Several high-k materials are utilized as gate oxide. We find that the performance of the proposed DMG-GOS JLFinFET is enhanced in terms of subthreshold swing (SS), Ion/Ioff and Drain induced barrier lowering (DIBL) when high-k materials are utilized to replace gate oxide and spacers. According to the simulation results, materials with high dielectric constants produce favorable electrical properties. Furthermore, this technology is useful for low power applications. Additionally, using an insulation material with a high-k value raises the ON current, which increases the device's flexibility. It has been observed that, among all higher dielectric single-k spacers (Air, Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf> , HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> ), with HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> spacer better performance is achieved.