Abstract
Power dissipation has become a major concern in VLSI circuit design with the rapid launch of battery powered applications. In high-performance constructions, the leakage component of power consumption is comparable to the switching component. This percentage increases as the technology scales unless effective leak control techniques are in place. In the case of fault-tolerant applications it is also not necessary to adhere to the exact calculation method. Therefore, an approximate multiplier of 8 x 8 is developed in this article using several proposed techniques to reduce leakage power such as MTCMOS, DUAL-Vt, and LECTOR. All of the above techniques are simulated with a tanning tool using 90 nm technology.
Highlights
Approximate Computing (AC) is a wide range of techniques that reduce the precision of a computation to improve performance, power, and / or other quality metrics
Power dissipation is an important consideration in VLSI CMOS circuit design
One of the main contributors for the static power consumption is sub-threshold leakage current, the drain to source current when the gate voltage is smaller than the threshold voltage
Summary
Approximate Computing (AC) is a wide range of techniques that reduce the precision of a computation to improve performance, power, and / or other quality metrics. Supply voltage scaling has remained the major focus of the low power design This has resulted in circuits operating at a supply voltage lower than the threshold voltage of a transistor (i.e. subthreshold region). Multi-threshold CMOS (MTCMOS) is a design technique in which high threshold sleep transistors are connected between the logic circuit and power or ground, creating a virtual supply rail or virtual ground rail, respectively. The low threshold voltage transistors which have high performance are used to reduce the propagation delay time in the critical path. There are methods high threshold voltage (HTV) is assigned to transistors of some gates in the non-critical paths while specifying the low-threshold voltage for the gates in the critical path In this technique, no additional transistors are required as in the case of multithreshold voltage technique. Reduction of static power is achieved while maintaining the same performance as single threshold voltage circuit [6], [7]
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