Abstract
The paper proposes a low latency BCH decoder with low complexity using parallel computation and simplifying locating errors by finding the roots of the affine polynomial over finite fields. The proposed design can be implemented on low-cost hardware platforms while applicable in very low latency information systems.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
