Low impedance characterization of power delivery network on substrate level for high speed digital applications

Abstract

This paper describes an effective characterization technique developed for low impedance extraction of the power delivery network (PDN) in today's high-speed digital applications. Sub-milliohm impedances across almost DC to tens of MHz can be measured accurately on a microprocessor substrate with cutting edge design of the decoupling scheme. Compared to the conventional solutions of getting transfer-impedance obtained by 2-port vector network analyzer (VNA) measurement data, gain-phase test port provided by commercial RF network analyzer is utilized due to its ground loop error elimination architecture. An exercise to optimize locations of excitation probing point and receiving probing point is shown to minimize potential spurious coupling through via loops in a typical flip chip substrate. The accuracy of this low impedance characterization method is further demonstrated by first order modeling of the equivalent series resistance (ESR) & equivalent series inductance (ESL) of a PDN with surface-mounted and embedded discrete chip capacitors.