Impedance Characterization of Power Delivery Network in a Flip Chip Package on a Printed Circuit Board

Abstract

This paper discusses low impedance characterization techniques used for power delivery network (PDN) in today's high-performance digital systems. More importantly, sensitivity analysis is presented to study impact of measurement accuracy against landing locations of probes onto a flip chip package and more specifically relative distance between two micro-probes in S21 measurements by vector network analyzer (VNA). Milliohms impedances across wide bandwidth, from approximately DC to GHz frequency range, can be measured accurately and well-correlated with simulation data on a microprocessor micro PGA substrate sitting in a socket mounted onto a printed circuit board (PCB) with cutting edge design of capacitive decoupling scheme. Conventionally, transfer-impedance obtained by two-port VNA measurement is used for PDN characterization. Being challenged by accessibility of test points in a complex package and board design, closely landing of the two micro-probes onto C4 pads would induce unwanted measurement noise caused by inductive coupling while excessive distance between the two micro-probes would result into artificial low impedance caused by parasitic inductance in the power planes of the package. Cautious arrangement of probing scheme in measurement that mimic to port setting in simulation is crucial in low impedance characterization of PDN at frequency range of interested. The accuracy of this low impedance characterization with optimized probing locations is verified by analytic calculation and simulation