Low energy pipelined Dual Base (decimal/binary) Multiplier, DBM, design

Abstract

Combined binary/decimal arithmetic is optimal in supporting binary and decimal high speed and low power applications. A low energy clock-gated pipelined dual base binary/decimal fixed-point multiplier is suggested extending a previously proposed non-pipelined design. A thorough study conducted on both the pipelined and non-pipelined designs versus other architectures in literature proves tremendous reductions in power, energy and area consumption. The non-pipelined multiplier design saves energy and area consumptions by up to 41% and 37%, respectively, retaining almost the same delay as the fastest known design in literature. It also allows operating frequencies of up to 4GHz for 15nm technology. Then, the pipeline stages are chosen to achieve further energy reductions with acceptable latency. In addition, clock gating the pipelined multiplier design is introduced to provide a total of 43% energy reduction for the pipelined design if compared to the non-pipelined design.