Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation

Abstract

In this paper, two Low cost and Soft Error Hardened latches (referred to as LSEH1 and LSEH2) are proposed and evaluated. The proposed latches are fully SEU immune, i.e. they are capable of tolerating all particle strikes to any of their nodes. Moreover, they can mask Single Event Transients (SETs) occurring in combinational logics and reaching the input of the latches. We have compared our SEU/SET-tolerant latches with some well-known previously proposed soft error tolerant latches. To evaluate the proposed latches, we have done a set of SPICE simulations. The simulation results trough comparisons with other hardened latches reveal that the proposed latches not only have more robustness but also they have the advantage of lower cost in terms of power, area, and delay. Moreover, since process and temperature variations have a considerable effect on today’s VLSI circuits, we have precisely investigated the effect of process variations such as threshold voltage and W/L variations on the delay and power consumption of our proposed latches.