An Energy-efficient Circuit Technique for Single Event Transient Noise-Tolerance

Abstract

Presented is a circuit technique that mitigates the impact of single event transient (SET) noise in deep submicron (DSM) circuits with minimal speed, power and area penalty. The technique combines a novel dual-sampling flip-flop (DSFF) and a skewed CMOS (SCMOS) circuit style. The DSFF and SCMOS are designed to eliminate, respectively, SETs with polarity of 1-0-1 and 0-1-0. We present a case study of inverter chain circuits in a typical 0.18 /spl mu/m process under the influence of radiation induced soft errors. We quantify the SET-tolerance of the proposed technique by simulating the circuits' soft error rate (SER) using a recently developed tool, SERA (soft error rate analyzer). The results show that the DSFF latches the input without any speed penalty compared to a conventional flip-flop, if no soft error has occurred. Otherwise, the DSFF alone eliminates the 1-0-1 SETs while incurring a worst-case speed and power penalty of 310 ps and 39 /spl mu/W/GHz, respectively. The proposed technique can completely eliminate the impact of SETs with both polarities when tuned appropriately.