Low-C ESD Protection Design With Dual Resistor-Triggered SCRs in CMOS Technology

Abstract

The electrostatic discharge (ESD) protection design with low parasitic capacitance seen at I/O pad is needed for high-frequency applications. Conventional ESD protection designs with dual diodes or dual stacked diodes have been used for gigahertz applications. To further reduce the parasitic capacitance, the ESD protection design by using complementary resistor-triggered silicon-controlled rectifiers (RTSCRs) is proposed in this paper. The proposed design includes a P-type RTSCR between I/O and ${{V}}_{{DD}}$ , an N-type RTSCR between I/O and ${{V}}_{{SS}}$ , and a power clamp circuit between ${{V}}_{{DD}}$ and ${{V}}_{{SS}}$ to achieve whole-chip ESD protection. Verified in silicon chip, the RTSCRs have the advantages, such as the sufficient low clamping voltage and lower parasitic capacitance, as compared with the conventional ESD protection designs. Therefore, the proposed design is suitable for low-C ESD protection in CMOS technology.