Loopback Virtual Channel Router Architecture for Network on Chip

Abstract

Low-level design parameters - such as router micro-architecture, switching techniques and packet sizes - have a huge impact on performance and cost of Network on Chip (NoC) implementation. This work proposes a router micro-architecture that has a mechanism for buffer structure, allocation, and arbitration, which minimizes latency, area overhead of the router, and power consumption. The proposed router micro-architecture can be adapted to various switching techniques used in current NoC implementations, and is independent of the topology. The architecture was developed, simulated, and synthesized using hardware description language (HDL). The performance of the architecture was evaluated for hotspot congestion scenarios and compared to classical router micro-architectures. Compared to classical router micro-architectures, this architecture achieves better performance for area, latency and power.