A comparative study of input port and crossbar configurations in NoC router microarchitectures

Abstract

Network-on-Chip (NoC) has emerged as a promising solution as an on-chip interconnect for multi-cores. Most of the research in NoCs revolves around router microarchitecture for power efficiency and performance and in algorithms for efficient data transfer. While many works in the literature discuss the impact of buffer organization on the performance in terms of latency, in this work we evaluate the impact of buffer organization with area and power consumption in the router. In this experimental study, we implement 36 different router architectures with different flit sizes, input port and crossbar configurations. All these router architectures are implemented, synthesized and validated on the 28nm Xilinx Kintex KC705 FPGA hardware for comparison. We have also synthesized these routers using the 1P8M UMC65nm standard cell technology on Cadence ASIC flow. We report that for the same number of buffers, the dynamic power and area can vary by up to 67% based on the configuration. We also find that increasing the number of buffers does not increase area and power by the same proportion. Further we report that the crossbar configuration can be significantly improved by designing routing specific crossbars.