Logical effort model extension with temperature and voltage variations

Abstract

The method of ldquoLogical Effort Delay Modelrdquo allows designers to quickly estimate delay time and optimize logic paths. But the previous variances of logical effort models do not mention how to handle process, voltage, and temperature (PVT) variations appropriately, which may induce a serious misestimate. According to simulation results, delay time increases 21% while temperature increasing from 0degC to 125degC, and increases 2X while supply voltage decreasing from 1 V to 0.5 V in 90nm process. Thus a simple linear extended logical effort g, 1/g=(m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> t+b <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> )V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> +C, supporting for temperature t and supply voltage VDD variations is presented. The proposed model enables designers to estimate the logic path delay and to optimize an N-stage logic network under different temperature and supply voltage conditions. After validation, the accuracy of this new extended logical effort model can achieve about 90%.