Abstract
The behaviour of a defective CMOS latch cell with floating gate defects is analysed in order to investigate the detection of these defects by logic testing. A large number (40%) of the defects will never be detectable by logic testing. Some of the remaining floating gate defects are also undetectable by logic testing, depending on their defect topologies. The need for other test methods such as IDDQ or delay testing is discussed.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have