Bridging fault simulation using Iddq, logic, and delay testing

Abstract

Accepted integrated circuit verification techniques involve stuck-at fault simulation. However, it has been shown that the majority of actual physical faults in the faulty integrated circuit are bridging faults. For this reason, the interest in bridging fault simulation techniques have increase. One characteristic with bridging faults is that the bridging fault may have electrical as well as logical behavior. This characteristic makes detection of bridging faults more difficult and this characteristic increases the complexity of bridging fault simulation. The three techniques most widely used for bridging fault simulation are current testing, stuck-at testing, and delay testing. This paper compares the complexity and robustness of the three techniques and new developments in the three techniques. Results show the current testing technique to be the most robust and have the lowest complexity which approaches stuck-at fault simulation complexity.