Logic simulation methods for longest path delay estimation

Abstract

Two original methods are proposed for digital circuit delay estimation with logic simulation: direct circuit simulation (DCS) and inverse circuit simulation (ICS). With only one run of the logic simulator the DCS method evaluates the longest path delay for each signal in the circuit for both rising and falling edges. If the delay to some primary output is too long to meet with required circuit operating frequency, the ICS method can be applied to extract that portion of the circuit that is subject to redesign and delay minimisation. Both methods are very fast and suitable for interactive use during the logic verification phase of the design process. While the ICS method can be easily implemented in modern hardware description languages such as VHDL or VERILOG, for the implementation of the DCS method a simple, yet effective, general signal attribute modelling mechanism is proposed. Both methods are implemented in AleC++, the input language of the simulator ALECSIS, and their efficiency is shown on a set of ISCAS'85 benchmark circuits.