Inverse circuit simulation method for topological delays estimation with logic simulator

Abstract

In this paper an original method is proposed for digital circuit topological delays estimation which is based on standard logic simulation mechanisms. The inverse circuit simulation (ICS) method is intended for interactive use in conjunction with circuit logic verification. Inverse circuit model propagates signal transitions in inverse direction: from circuit outputs toward circuit inputs. One simulator run provides the longest path delay for a chosen, rising or falling, edge at one circuit output. At the same time, the part of the circuit is detected which is the subject of redesign or delay optimization if the longest path delay does not satisfy required circuit operating frequency. Due to path reconvergence delay overestimation can occur which can be measured at each signal and propagated through the circuit together with logic states. The efficiency of the proposed method is tested on ISCAS '85 benchmark circuits.