Local Bit-Line SRAM Architecture With Data-Aware Power-Gating Write Assist

Abstract

In this brief, a local bit-line (LBL) SRAM with data-aware power-gating write assist is proposed for near-threshold operation. The proposed SRAM achieves high read stability and write ability by adopting LBL architecture and power-gating transistors, respectively. Depending on the input data, one of the power-gating transistors is adaptively cut off, which eliminates the write disturbance from the power supply. Thus, reliable write operation can be performed. The proposed SRAM achieves a read stability yield of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.12{\sigma }$ </tex-math></inline-formula> , write ability yield of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.26{\sigma }$ </tex-math></inline-formula> , and consumes 0.21 pJ energy/operation with 58% shorter read delay and 33% smaller area per bit than the 12T SRAM at a supply voltage of 0.4 V in a 22-nm FinFET process.