Performance and Reliability of Asymmetrical Underlapped FinFET based 6T and 8T SRAMs in Sub-10nm Domain

Abstract

In this paper, the performance and reliability of optimized 6T and 8T SRAM circuits using high I ON /I OFF ratio Asymmetrical Underlapped FinFETs are determined at a reduced supply voltage of 500mV. Performance of both SRAM designs are evaluated during read and write operations. 6T SRAM achieves 44.97% improvement in the read energy compared to 8T SRAM. However, 6T SRAM write energy degraded by 3.16% compared to 8T SRAM. Read stability and write ability of SRAM cells are determined using Static Noise Margin and N-curve methods. Moreover, Monte Carlo simulations are performed on the SRAM cells to evaluate process variations. Simulations were done in HSPICE using 7nm Asymmetrical Underlap FinFET technology.