Abstract

The LinoSPAD camera system is a modular, compact and versatile time-resolved camera system, combining a linear 256 high fill factor pixel CMOS SPAD (single-photon avalanche diode) sensor with an FPGA (field-programmable gate array) and USB 3.0 transceiver board. This modularization permits the separate optimization or exchange of either the sensor front-end or the processing back-end, depending on the intended application, thus removing the traditional compromise between optimal SPAD technology on the one hand and time-stamping technology on the other hand. The FPGA firmware implements an array of 64 TDCs (time-to-digital converters) with histogram accumulators and a correction module to reduce non-linearities. Each TDC is capable of processing over 80 million photon detections per second and has an average timing resolution better than 50 ps. This article presents a complete and detailed characterization, covering all aspects of the system, from the SPAD array light sensitivity and noise to TDC linearity, from hardware/firmware/software co-design to signal processing, e.g., non-linearity correction, from power consumption to performance non-uniformity.

Highlights

  • Many time-resolved applications can benefit from a compact, versatile, and simple-to-use single-photon detector

  • CMOS SPADs have existed since the early 2000s and they are on their way to replace photomultiplying tubes (PMTs) and multi-channel plates (MCPs) in many applications requiring high compactness, large pixels counts, high robustness and reliability [4,5]

  • A CMOS SPAD is an ordinary diode in a standard microelectronic circuit, which is reverse biased above its breakdown voltage

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Summary

Introduction

Many time-resolved applications can benefit from a compact, versatile, and simple-to-use single-photon detector. CMOS SPADs (single-photon avalanche diodes) have existed since the early 2000s and they are on their way to replace PMTs and MCPs in many applications requiring high compactness, large pixels counts, high robustness and reliability [4,5]. More recent developments include the 2 × 256 array of Krstajić et al [14], the 2 × 128 array of Nissinen et al [15], and the 8 × 1024 array by Maruyama et al [16], targeting respectively time-resolved fluorescence and Raman spectroscopy These examples include processing electronics in the sensor itself and produce streams of timestamps, histograms, and/or fluorescence lifetime information. LinoSPAD combines a technologically conservative SPAD sensor front-end with an advanced processing back-end through a field-programmable gate array (FPGA), in a novel way.

LinoSPAD: A Versatile SPAD Line Sensor
Sensor Architecture
FPGA Interface Card
FPGA Architecture
Global Architecture
Clock Architecture
Event Counter Array
TDC Core
Histogram Accumulation
Histogram Processing
FPGA Implementation
Breakdown Voltage
Power Consumption
TDC Response
Temperature Effects in SPAD Sensors
Post-Processing
Histograms
Performance Summary and Comparison to other FPGA TDCs
Extended Non-Linearity Characterization and Fabrication Variations
Dead Time and Afterpulsing
TDC-to-TDC Variation
Sensor-to-Sensor Variation
FPGA-to-FPGA
Findings
Conclusions
Full Text
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