Abstract

Per-pixel time-to-digital converter (TDC) architectures have been exploited by single-photon avalanche diode (SPAD) sensors to achieve high photon throughput, but at the expense of fill factor, pixel pitch and readout efficiency. In contrast, TDC sharing architecture usually features high fill factor at small pixel pitch and energy efficient event-driven readout. While the photon throughput is not necessarily lower than that of per-pixel TDC architectures, since the throughput is not only decided by the TDC number but also the readout bandwidth. In this paper, a SPAD sensor with 32 × 32 pixels fabricated with a 180 nm CMOS image sensor technology is presented, where dynamically reallocating TDCs were implemented to achieve the same photon throughput as that of per-pixel TDCs. Each 4 TDCs are shared by 32 pixels via a collision detection bus, which enables a fill factor of 28% with a pixel pitch of 28.5 μm. The TDCs were characterized, obtaining the peak-to-peak differential and integral non-linearity of −0.07/+0.08 LSB and −0.38/+0.75 LSB, respectively. The sensor was demonstrated in a scanning light-detection-and-ranging (LiDAR) system equipped with an ultra-low power laser, achieving depth imaging up to 10 m at 6 frames/s with a resolution of 64 × 64 with 50 lux background light.

Highlights

  • The demand for 3D imaging systems is growing rapidly, with applications such as facial recognition, robotics, bioimaging, and LiDAR

  • We presented a 32 × 32 singlephoton avalanche diode (SPAD) imager, fabricated in a 180 nm CMOS technology, where each 32 pixels in one column are connected to a collision detection bus

  • The events are read off-chip in an event-driven readout method with high energy efficiency, where 32 channels are employed operating at a bandwidth of 5.12 Gbps, which enables a maximum throughput of 222 million counts per second (Mcps) and 465 Mcps in photon timestamping (PT) and photon counting (PC) mode, respectively

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Summary

A CMOS SPAD Imager with Collision Detection and

Chao Zhang 1, *,† , Scott Lindner 2,3,† , Ivan Michel Antolovic 3 , Martin Wolf 2 and Edoardo Charbon 3,4. Quantum and Computer Engineering, Delft University of Technology, Mekelweg 4, 2628CD Delft, The Netherlands. Advanced Quantum Architecture Laboratory, École Polytechnique Fédérale de Lausanne (EPFL), Route. Received: 5 October 2018; Accepted: 15 November 2018; Published: 17 November 2018

Introduction
Sensor Architecture
Pixel Schematic and Collision Detection Bus
Dynamic Reallocation of Time-to-Digital Converters
Synchronizers
Chip Realization
Chip Pixel Characterization
DCR measurement excess bias voltage of the whole array is shown in
TDC Characterization
Flash 3D Imaging
17. Areflectivity
10 K photons detected was at each scanning enabling
Proposed Background Light Suppression Architecture
Conclusions

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