Lateral DMOS With Partial-Resist-Implanted Drift Region for Alleviating Hot-Carrier Effect

Abstract

Maximum operating gate voltage ( ${\mathbf{V}}_{\mathbf{gmax}} $ ) stress is observed and confirmed as the worst hot-carrier degradation condition for the lateral double-diffused MOS (LDMOS) with multiple floating poly-gate field plates. To reduce the worst degradation, an improved N-drift region implantation method called a partial-resist-implantation is proposed for the LDMOS. It shows that the electrical fields and impact ionization generation rates at the degradation-sensitive positions (beneath the bird’s beak and the edge of real poly-gate) have been obviously decreased. The measured data demonstrate that the degradation of on-resistance for the improved device is reduced by 13.5% after 3000 s ${\mathbf{V}}_{\mathbf{gmax}} $ stress. The charge pumping experiment has also verified the validity of the method.