Latch-up issue of drain metal connection split in test circuit with 3D TCAD simulation analysis in CMOS application

Abstract

In CMOS integrated circuit (IC), parasitic Silicon-Controlled Rectifier (SCR) path is unavoidable and causes the risk of latch up (LU) issue. In this work, we found that the SCR characteristic would be influenced by the difference of drain metal connection so it would affect the result of LU measurement. Two common test circuits were measured and discussed in the paper. Additionally, 3D TCAD simulations are performed to help the analysis. Finally, holding voltage (Vh) is increased from 1.5 V to 2.0 V and holding current (Ih) is increased from 0.25A to 0.75A with higher leakage current (IL), lower trigger voltage (Vt1) in drain-connection circuit. Therefore, drain-disconnection circuit, which is simulated as minimum spacing SCR path between two nearby circuits in IC design, is worse case that makes us judge the LU risk much rigorously.