Large Die Size Lead Free Flip Chip Ball Grid Array Packaging Considerations for 40nm Fab Technology

Abstract

To reduce the RC latency, leading edge silicon nodes employ porous SiO2 dielectrics in the interconnect stack. Introduction of porosity lowers the dielectric constant, k, but also significantly decreases both the elastic modulus and fracture toughness of the dielectric. As such, devices manufactured in silicon processes that use low K (90nm, 65nm, and 55nm) and even more so extremely low K ( 45nm, 40nm, and 28nm) interlayer dielectrics are substantially more prone to fracture as a result of package induced stresses than non porous higher K dielectrics. Since the package stresses scale with die size and package body size and inversely with bump pitch, manufacture of large die and package size flip chip devices made with extremely low K dielectrics has proven to be challenging. The stress challenge is further exacerbated by the RoHS requirements for lead free packaging which requires higher process temperatures and somewhat higher yield point solders. The combination of increased stress and reduced mechanical robustness of porous dielectrics has lead to significant reliability and assembly yield issues that have in some cases slowed the introduction of 45nm and 40nm large die lead free flip chip into the market. The work summarized in this paper shows that devices designed to withstand stresses in combination with appropriate assembly processes and bill of materials, yield highly reliable, lead free flip chip packaged devices, with die sizes greater than 400mm2 and package sizes greater than 42.5mm on a side in commercial assembly production lines.