Joint Use of Methods of Structural Decomposition for Optimizing the Circuit of Moore FSM

Abstract

A method is proposed for optimizing hardware expenditure in the Moore FSM circuit implemented with FPGA. The method is based on joint input replacement use and transformation of state codes into codes of classes of pseudoequivalent states. This approach leads to a three-level FSM circuit. An example of synthesis of a Moore FSM with application of the proposed method is shown. Analysis of positive and negative features of the proposed method is constructed. The researches based on standard benchmark FSMs show that the proposed method allows reducing hardware expenditure and consumed power with insignificant amount of degradation of FSM performance.