Hardware Reduction in Logic Circuits of Moore FSM

Abstract

AbstractThe Chapter is devoted to the problems of optimization of Moore FSM logic circuits implemented with FPGAs. The general characteristic is given for methods of functional and structural decomposition. Distinctive features of FPGA are analyzed allowing the number of look-up table (LUT) elements in logic circuits of Moore FSMs to be decreased. The classification of optimization methods are given for Moore FSM including: (1) the transformation of state codes into codes of the classes of pseudoequivalent states (PES); (2) presentation of state codes as concatenations of codes of PES and collections of microoperations; (3) replacement of logical conditions (input variables of FSM) by additional variables. All discussed methods are illustrated by examples. The chapter is written together with PhD student Olena Hebda (University of Zielona Gora, Poland).KeywordsImplement Logic CircuitsHardware ReductionPseudoequivalent States (PES)Look-up Table (LUTs)Input Memory FunctionsThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.