Implementing Control Algorithms with FPGAs

Abstract

The chapter is devoted with FPGA-based implementing control algorithms represented using the language of graph-schemes of algorithms. We use models of Mealy and Moore finite state machines (FSM) to design the circuits of control units. We start from single-level FSM circuits implemented using look-up table (LUT) elements and/or embedded memory blocks (EMB). These methods are illustrated using standard benchmark FSMs. Next, the methods of structural decomposition are discussed. We discuss how to reduce hardware using the replacement of logical conditions, encoding the collections of microoperations, encoding the terms, and transformation of objects. We show how to use the pseudoequivalent states for optimization of logic circuits of Moore FSMs. The third section is devoted to hardware reduction of Moore FSMs targeting the replacement of logical conditions. At last, we discuss how to optimize hardware replacing state registers by state counters. The discussed methods target control units based on models of Moore FSMs.