VLSI-based Logic Synthesis

Abstract

AbstractThe chapter deals with analysis of methods of logic synthesis targeting VLSI. It starts with analysis of evolution of logic elements. The peculiarities of synthesis are shown for PROMs, PLAs, and PALs. Next, three classes of VLSI chips are considered, namely ASIC, CPLD and FPGA. The methods of structural decomposition are discussed. Main idea of these methods is reduced to diminishing the numbers of literals in systems of Boolean functions due to increasing the number of logic levels in FSM circuits. Methods of replacement of logical conditions and encoding of collections of microoperations are analysed. Next, these methods are applied for reducing hardware in ASIC, CPLD and FPGA-based FSM circuits. It is shown that memory blocks allow implementing systems of regular Boolean functions. The methods basing of classes of pseudoequivalent states are discussed for Moore FSM. There are shown VLSI-based structural diagrams of FSM circuits based on different methods of structural decomposition.