Jitter Modeling in Digital CDR with Quantization Noise Analysis

Abstract

Phase rotator-based digital clock and data recovery (CDR) using multi-level bang-bang phase detector (ML-BBPD) and time to digital converter (TDC) is analyzed at system and circuit level. A model is proposed for calculating the quantization noise and bit error rate (BER), in order to evaluate the important parameters in CDR design. The jitter analysis is done based on the probability density function achieved from the quantization noise error of the BBPD and TDC. The analysis of ML-BBPD is shown that by increasing the number of sampling clocks, the quantization noise and consequently the jitter and BER are significantly reduced. Also, it is shown that by improving the resolution of the TDC and increasing number of delay cells for the purpose of keeping fixed the dynamic range, the output jitter of TDC is decreased. In the proposed model and also simulation, it is approved that by increasing the ratio of RMS input Gaussian jitter to the quantization step, the output jitter reaches to its saturated value. To prove the jitter model, the goodness of fit test based on Kolmogorov–Smirnov test is used and in addition, the simulation is provided for circuit level CDR. The circuit level simulation is done in TSMC 65 nm CMOS technology. The CDR is worked under 1 V supply voltage at 480Mbit/s bit rate useful for USB2 applications. The CDR dissipates 913 µW power and generates 0.258 ps RMS jitter, while it occupies 166 µm × 104 µm chip area.