Abstract

Historically, it has been common to treat design for testability (DFT) independently of design for reliability (DFR) and design for yield (DFY). DFT is viewed as an add-on to the standard design process — something that happens in parallel with design, but off the main path. DFR is seldom considered at all during the design process, with the exception of ESD circuitry, another add-on late in chip development. DFY is vague and mysterious to all but those involved in the deepest levels of physical design, and even those individuals do not always recognize that the source of their design rules is DFY.

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