Modelling economics of DFT and DFY: a profit perspective

Abstract

Because of the rapid increase in the complexity of VLSI circuits, a yield of 100% is virtually impossible. The problem rises intuitively: how can design for testability (DFT) and design for yield (DFY) be combined so as to save money? This question must be dealt with today for SOC designs at an early stage of the design cycle. To address this problem, a profit-evaluation system (PES) for IC designers is proposed from the business perspective. This system will help designers to determine the yield and test plan when a specified quality level is given. The type of circuit fabric and raw manufacturing data (i.e., wafer size, wafer cost, defect density and distribution) are given for the system. The outputs of the system are the values of yield and fault coverage that generate the maximum profit. Different yield models and cost models are selectable by the user. Experimental results show that the system can find the optimal yield and test plan for generating the maximum profit.