(Invited) Impact of Processing Factors on the Low-Frequency Noise of Gate-All-Around Silicon Vertical Nanowire FETs

Abstract

Future CMOS technology nodes will rely on Gate-All-Around (GAA) FETs with ultimate control over the short-channel effects. In this class of devices, GAA Vertical Nanowires (VNWs) offer some clear integration advantages over horizontal architectures. In addition, some operational parameters are also favourable, like, the low-frequency (LF) noise, as shown recently [1]-[3]. In this work, an overview will be given of the impact of certain processing factors on the noise spectrum and magnitude of silicon GAA VNW FETs.Silicon NWs with a diameter of ~45 (50) nm have been epitaxially grown on either bulk or Silicon-On-Insulator (SOI) substrates. They are either undoped (intrinsic) or in-situ B/P-doped (p/nMOS), resulting in the latter case in a Junctionless (JL) structure. For the “bulk” devices an in-situ B-doped (or P-doped) silicon back contact has been deposited as source electrode, while an in-situ B-doped SiGe source was grown on SOI (pFETs). In both cases, a highly B-doped SiGe (or P-doped silicon) drain was deposited on the 90 nm long NWs to reduce the series resistance. LF noise measurements have been performed as described elsewhere [1],[2], in linear operation (|VDS|=0.05 mV), for a current range from about 10 nA to a few mA. Spectra have been recorded in Forward (F) mode or in Reverse (R) mode, with source and drain switched.The impact of the width of the RMG cap, shown in Fig. 1 on the F noise of GAA VNW nFETs has been reported before [1], showing that the use of a wide cap results in a lower input-referred voltage noise PSD (SVG) (Fig. 2). The asymmetry in SVG at f=10 Hz in F and R operation of GAA VNW pFETs is represented in Fig. 3 (bulk source) and Fig. 4 (SOI). While significantly lower noise is observed in R operation for “bulk”, insignificant differences are seen for the SOI pFETs. At the same time, the PSD is generally lower for the bottom source (bulk) compared with a SiGe source on SOI (Fig. 5). More detailed analysis reveals that the 1/f noise is dominated by mobility fluctuations (Dm) for VNW pFETs on bulk substrates [2]. The situation is more complicated for SOI pFETs a shown in Fig. 6 and depends on the channel doping density. In weak inversion (low ID), either Dn or Dm fluctuations can prevail. At higher ID, access resistance (RS) starts to dominate the 1/f noise behaviour. Finally, also the in-situ B doping density plays a significant role in the LF noise mechanism of the JL channels (Fig. 6), offering several technology knobs to optimize the 1/f noise performance.[1] E. Simoen, A. Chasin, P. Matagne, E. Rosseel, A. Hikavyy, R. Loo, P. Favia, H. Bender, E. Vancoille and A. Veloso, ECS Trans., 97 (5), pp. 59-64 (2020).[2] E. Simoen et al., submitted to Solid-State Electron.[3] T. Imamoto, Y. Ma, M. Muraguchi and T. Endoh, Jpn. J. Appl. Phys., 54, p. 04DC11 (2015). Figure 1