Novel Y-function based strategy for parameter extraction in S/D asymmetric architecture devices and low frequency noise characterization in GAA Si VNW pMOSFETs

Abstract

In this work, DC and low frequency noise measurements are performed in p-channel gate-all-around (GAA) silicon vertical nanowire (Si VNW) MOSFETs. The DC measurements highlight asymmetry in the drain current and transconductance transfer characteristic even in linear operation, at an applied drain voltage of −50 mV. A novel Y-function based strategy for parameter extraction in S/D asymmetric devices is proposed. This novel strategy allows the estimation of the value of each access resistance, from source and from drain sides, respectively, and allows overcoming the device asymmetry to provide an accurate extraction of the main DC parameters. The low-frequency noise studies on forward and reverse operation mode, demonstrate that the 1/f noise in both modes can be explained by the correlated carrier number (Δn) and mobility fluctuation (Δμ) mechanisms, with additional contribution of the access resistance noise in strong inversion.