Investigation on negative capacitance FinEFT beyond 7 nm node from device to circuit

Abstract

In this study, a SPICE model for Negative Capacitance FinFET (NC-FinFET) based on the BSIM-CMG model and Landau-Khalatnikov (L-K) equation is developed. The areas of the ferroelectric layer (AFE) and the work functions (WFs) of n-NC-FinFET and p-NC-FinFET are adjusted to reduce the shift of the threshold voltage. As a result, the NC-FinFET-based seven-stage ring oscillator (RO) has a smaller delay, and energy can down to 72.2 % compared with the FinFET-based RO under the same delay. Furthermore, the NC-FinFET-based 6T SRAM has a smaller read and write time and lower static power than the FinFET-based 6T SRAM. Besides, under two key parameters (the length of the gate (Lg), the width of gate (Wfin), of NC-FinFET), the NC-FinFET-based 6T SRAM has great advantages in static power, read and write time. Therefore, the research on NC-FinFET from the device to the circuit can provide meaningful guidance for the further application of NC-FinFET.