Investigation of Program Saturation in Scaled Interpoly Dielectric Floating-Gate Memory Devices

Abstract

This paper investigates the program saturation in aggressively scaled interpoly dielectric (IPD) floating-gate (FG) cells for nand application. To describe the program saturation in IPD stacks containing thick suboxides (ges 4 nm) , a simple model was developed, directly yielding the maximum reachable programmed threshold voltage level for a given FG cell geometry. The presented model agrees very well to program saturation measurements carried out on a 48 nm FG nand technology with an IPD composed of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> . By extending the considerations to an arbitrary IPD, this paper represents the first attempt to quantify the IPD current blocking ability required for future scaled FG memory cells.