A novel planar floating-gate (FG) / charge-trapping (CT) NAND device using BE-SONOS inter-poly dielectric (IPD)

Abstract

Although planar floating gate (FG) device using high-K IPD has been proposed, our study indicates that out tunneling through IPD due to the high electric field is inevitable, leading to programming/erasing saturation. Moreover, charge trapping in IPD is a major concern. In this work, we propose a completely different approach - using a trapping IPD for storage. Our concept is to combine the merits of CT and FG - CT for good retention and scaling to few-electron regime and FG for edge effect immunity and faster erase. The planar “fusion” FG/CT devices are fabricated by replacing the conventional IPD ONO of a FG device by a CT BE-SONOS structure. Both simulation and experimental results indicate that most of the stored electrons are trapped inside the SiN trapping layer instead of the FG. The CT storage provides excellent retention even for a very thin tunnel oxide (≪5nm). On the other hand, the thin FG provides an equipotential channel that screens any non-uniform injection effect. Excellent memory window, scalability and reliability are demonstrated.