Investigation of process-induced performance variability and optimization of the 10 nm technology node Si bulk FinFETs

Abstract

we propose a process and device design strategy for Lg=14nm Si bulk n/p-FinFETs based on the effects of process-induced geometry variability on device performance. A calibrated TCAD simulation was used to design and optimize structures and these were also tested under various process split conditions. By comparing the I–V data from process-changed devices with nominal CMOS, relationships between process- induced geometry variation and device performance were investigated and analyzed. Moreover a DC/RF compact model was executed to observe the geometry variability effects on ring oscillator and RF applications. Finally key circuit design factors to mitigate process variability are suggested.