Abstract
Monotonous increase of saturation drain current Id sat but linear-region drain current Id lin reduction during hot carrier injection (HCI) stress is observed in N-type Lateral Diffused MOSFET. But the phenomenon of Id sat increase is contrary to what we typically observed during HCI stress. The increase of Id sat has been attributed to the increase of saturation substrate current Ib sat after HCI stress. TCAD simulations showed that the lateral electric field increases under the high gate bias when a significant amount of electron trapping occurs along the STI corner in the drift region. The trapped electrons will change the distribution of localized electric potential and will result in the substrate current Ib increase. It is also observed that the 1st Ib peak at lower Vgs degrades, consistent with the reduction of drain and source current, due to HCI induced electron trapping. In another word, the electron trapping has two competing effects - one is with current degradation at lower Vgs and the other is with the electric field enhancement that causes the Id sat to increase at higher Vgs.
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