Investigation of Lanthanum Silicate Conditions on 4H-SiC MOSFET Characteristics

Abstract

The lanthanum silicate interface engineering has been shown to dramatically improve the mobility of 4H-silicon carbide (SiC) MOSFETs. We studied the impact of post deposition annealing (PDA) conditions and the initial lanthanum oxide (La <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) thickness on the MOSFET performance. The combination of 900 °C PDA and 1 nm La <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> leads to highest field-effect mobility. Higher PDA temperature leads to mobility reduction due to lower lanthanum concentration at the SiC/dielectric interface. The peak mobility and threshold voltage show strong dependence on the initial La <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> thickness.