(Invited) Control of Thermally-Grown SiO2/4H-SiC Mos Interface Properties and Its Impact on Mosfet Performances

Abstract

4H-SiC MOSFETs is extensively studied for high-voltage power device applications, however, the control of MOS interface properties have been one of the most challenging issues to meet the requirements of low on-resistivity and high-reliability. It is a challenging issue to reduce interface defect density at thermally oxidized SiO2/SiC interfaces since the thermal oxidation is inevitably accompanied with by a carbon-related product generation. We recently demonstrated that selective use of a high-temperature oxidation on 4H-SiC (0001) resulted in a significant improvement of MOS properties by a formation of a MOS capacitor with nearly-ideal CV characteristics and less interface state density (Dit) [1], even without introduction of nitrogen by NO annealing process. We consider high-temperature oxidation works to reduce the remaining carbon byproduct significantly [2]. We also investigated the impact of the post-deposition annealing (POA) conditions on interface state density. It was found that the POA at a relatively low temperature in O2 is quite effective to reduce Dit, probably due to the reduction of oxygen-deficiency induced defects. Employing sufficiently low temperature is so important to suppress further oxidation of the interface during POA. Thus appropriate selection of both POA time and temperature is inevitable to optimize the POA effects. We also found a significant decrease of near-interface oxide traps (NITs), which are the most possible origin of the slow responses of the electrical characteristics to the applied bias. After an optimization of the post-oxidation annealing processes in oxygen ambient at low temperature, the estimated density of NITs decreased by several times. Finally, a lateral-MOSFET on 4H-SiC (0001) was fabricated based on those process techniques. A relatively high effective mobility ~30 cm2/Vs, as a SiC MOSFET without nitridation of the interface, was obtained with the gate stack prepared simply by the combination of high-temperature thermal oxidation and post-oxidation annealing processes, while we can expecte a further improvement by applying the additional passivation techniques. The process design of thermal oxidation of SiC would be one of the promising ways to improve the MOSFET performance from the viewpoint of both the reduction of channel resistance and the improvement of device reliability. This work was partly supported by CSTI Cros-ministerial Strategic Innovation Promotion Program"Nex-generation power electrnonics" (funding agency: NEDO) and JSPS KAKENHI. [1] R. H. Kikuchi and K. Kita, Appl. Phys. Lett. 105, 032106 (2014).[2] H. Hirai and K. Kita, Appl. Phys. Express 8, 021401 (2015).