Investigation of Electrical Characteristics of Vertical Junction Si n-Type Tunnel FET

Abstract

In this paper, Si tunnel FETs (TFETs) with the vertical tunneling junction (nVTFETs) were demonstrated by utilizing fabrication processes compatible to those used for conventional Si MOSFETs. The vertical tunneling junction was realized by forming n-type surface pocket regions under gate overlap regions of p-type source extensions only using the ion implantation (I/I). The impacts of carbon (C) coimplantation and formation of offset spacer (OSS) on the TFET performance were examined. As a result, the performance of the fabricated nVTFETs was enhanced by applying the C coimplantation and the OSS formation before the I/I for the vertical tunneling junctions. It has been found, on the other hand, that nVTETs exhibit a reverse short-channel effect, where the threshold voltage increases with decreasing the channel length, and that this effect is correlated with the enhanced temperature dependence of subthreshold slope. These phenomena are attributable to the existence of a thermionic barrier between the source junction and the channel, formed by boron diffusion from the source region.