Introduction to High-k Gate Stacks

Abstract

The manifold aim of this chapter is: (1) to present a simple summary of the contents of the eleven other chapters of the book in a manner as continuous and cohesive as possible; (2) more importantly, to provide the basics, the definitions, simple explanations, and the missing links; (3) and to acclimatize the uninitiated reader. This chapter begins with an historical account going back some four decades when research was initiated into the Metal Oxide Semiconductor (MOS) tunnel diodes much ahead of its commercial adoption for nano-transistors. An introduction is then presented into the desirable characteristics of a current and future high-k gate stack followed by a discussion of the properties of the available and possible high-k candidates to replace the single SiO2 gate dielectric. The subsequent sections of the chapter deal with: (a) the basics, theory, and characteristics of the MOS structures and the MOS field effect transistor including its energy band diagrams, equivalent circuits, admittance-voltage and current–voltage characteristics, and parameter extraction methodologies; (b) the physics of the Hf-based gate stacks, which is the current favorite; (c) the processing of the Hf-based gate stacks including process optimization and control; (d) metal gate electrodes, work-function tuning, and metal gate integration; (e) the flat-band and threshold voltage anomaly including the role of the bottom and the top interface dipoles in this anomaly; (f) the channel mobility including the scattering mechanisms, the factors behind its degradation, and the options for attaining high mobility; (g) the mechanisms of gate stack degradation including fast and slow charge trapping and the reliability issues; (h) physics and technology of Ln-based gate stacks—perhaps the next generation; (i) the ternary higher-k gate dielectric materials including the roles of the structure modifiers and the higher-k phase stabilizers; (j) the crystalline high-k oxides including their novel applications; and (k) high mobility channels including their surface passivation and electrical characterization. This chapter concludes with a model for the figure of merit for evaluating the high-k material for gate stack application.